Processor Designer Tool Enables KYOCERA Design Team to Reduce Overall Project Schedule by Nine Months
Highlights:
- Synopsys’ ASIP design tools enable rapid exploration and optimization of processor architectures
- KYOCERA created a custom high-performance DSP in less than a year, saving an estimated nine months on their project schedule
- Automated creation of software development kit (SDK) and RTL design reduced engineering effort by about 75 percent compared to traditional manual processes
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced KYOCERA Document Solutions accelerated the design of a high-performance digital signal processor (DSP) for their next-generation multi-function printer using Synopsys’ application specific instruction-set processor (ASIP) design tools. By using tools that automate the design and optimization of application-specific processors, KYOCERA was able to develop a custom DSP that delivers the high performance required for complex image-processing functions in less than a year, saving an estimated nine months on their overall project schedule. In addition, unlike fixed hardware, the resulting ASIP provides the programmability and flexibility to meet the needs of multi-function printer image processing functions.
“ Synopsys’ reputation as an established provider of ASIP development tools and their multi-function printer design wins worldwide were key factors in our decision to use their ASIP design tools ,” said Michihiro Okada, general manager of the Software 3 R&D Division, Corporate Software Development Division at KYOCERA Document Solutions Inc. “ Being able to use a single processor description to design highly efficient RTL as well as the associated software development kit – including an optimizing C compiler –allowed us to focus on optimizing our architecture throughout the entire design process.”
Traditionally, each KYOCERA multi-functional printer model required the development of model-specific, fixed hardware system-on-chips (SoCs) to meet unique image processing algorithms and performance specifications. To improve development efficiency and lower total cost of ownership over the life of its next-generation printer products, KYOCERA required a more flexible and higher performance process or design with full programmability. After determining commercially available DSPs would not meet their performance goals, they selected Synopsys’ ASIP design tools to develop their own custom processor.
The ASIP solution from Synopsys enabled KYOCERA to use a high-level specification and quickly model multiple processor architectures, profile performance, and tune the architecture for their specific image processing application. Using this single input specification, Synopsys’ tool automatically generated the software development kit containing the instruction-set simulator (ISS), assembler, linker, debugger and C compiler, as well as the synthesizable RTL design.This not only enabled early software development and debugging, it also saved KYOCERA an estimated three-quarters of the effort of creating the SDK and RTL design compared to a traditional manual approach. The combination of early SDK availability and automation of architecture exploration and design creation resulted in a significant reduction in KYOCERA’s overall project schedule while producing a design optimized for their specific performance.
“By replacing fixed hardware with ASIPs, companies can save significant development effort and achieve their aggressive project schedules ,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “KYOCERA’s successful custom DSP implementation highlights how Synopsys’ ASIP tool technology enables designers to rapidly explore innovative processor architectures to achieve the best mix of programmability and performance, while greatly reducing their hardware and software development costs.”
